IDT71V432S5PFGI【PDF 6/18 页】IC SRAM 1MBIT 5NS 100TQFP

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IDT71V432, 32K x 32 CacheRAM

3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect

Synchronous Truth Table (1,2)

Address

Commercial and Industrial Temperature Ranges

Operation

Deselected Cycle, Power Down

Deselected Cycle, Power Down

Deselected Cycle, Power Down

Deselected Cycle, Power Down

Deselected Cycle, Power Down

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Write Cycle, Continue Burst

Write Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

Write Cycle, Suspend Burst

Write Cycle, Suspend Burst

Write Cycle, Suspend Burst

Used

None

None

None

None

None

External

External

External

External

External

External

External

Next

Next

Next

Next

Next

Next

Next

Next

Next

Next

Next

Next

Current

Current

Current

Current

Current

Current

Current

Current

Current

Current

Current

Current

CE

H

L

L

L

L

L

L

L

L

L

L

L

X

X

X

X

H

H

H

H

X

X

H

H

X

X

X

X

H

H

H

H

X

X

H

H

CS 0

X

X

L

X

L

H

H

H

H

H

H

H

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

CS 1

X

H

X

H

X

L

L

L

L

L

L

L

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

ADSP

X

L

L

X

X

L

L

H

H

H

H

H

H

H

H

H

X

X

X

X

H

H

X

X

H

H

H

H

X

X

X

X

H

H

X

X

ADSC

L

X

X

L

L

X

X

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

ADV

X

X

X

X

X

X

X

X

X

X

X

X

L

L

L

L

L

L

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

GW

X

X

X

X

X

X

X

H

H

H

H

L

H

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

L

H

L

BWE

X

X

X

X

X

X

X

H

L

L

L

X

H

H

X

X

H

H

X

X

L

X

L

X

H

H

X

X

H

H

X

X

L

X

L

X

BW X

X

X

X

X

X

X

X

X

H

H

L

X

X

X

H

H

X

X

H

H

L

X

L

X

X

X

H

H

X

X

H

H

L

X

L

X

OE (3)

X

X

X

X

X

L

H

L

L

H

X

X

L

H

L

H

L

H

L

H

X

X

X

X

L

H

L

H

L

H

L

H

X

X

X

X

CLK

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

↑

I/O

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

D OUT

Hi-Z

D OUT

D OUT

Hi-Z

D IN

D IN

D OUT

Hi-Z

D OUT

Hi-Z

D OUT

Hi-Z

D OUT

Hi-Z

D IN

D IN

D IN

D IN

D OUT

Hi-Z

D OUT

Hi-Z

D OUT

Hi-Z

D OUT

Hi-Z

D IN

D IN

D IN

D IN

NOTES:

1. L = V IL , H = V IH , X = Don’t Care.

2. ZZ = LOW for this table.

3. OE is an asynchronous input.

6.42

3104 tbl 07

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